A novel four quadrant CMOS analog multiplier

Analog multipliers are used in communication circuits, neural networks as well as frequency doublers and phase detectors. High linearity is the prime issue for multipliers in conventional applications like modulation circuits. Power consumption is the criteria in case of massive parallel processing based neural networks. This thesis details the design process of four-quadrant multiplier which could able to address the challenge mentioned above. A CMOS current mode four quadrant analog multiplier circuit is proposed. It is based on current mode squarer circuit; dual translinear loop is used for realizing the analog multiplier circuit. The circuit is designed and simulated. Eliminating the limitations of this configuration, four-quadrant multiplier based on complementary diode pair connection is designed and it shows better performance in terms of speed, low power and linearity.