Title :
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
Author :
Schafbauer, T. ; Brighten, J. ; Yi-Cheng Chen ; Clevenger, L. ; Commons, M. ; Cowley, A. ; Esmark, K. ; Grassmann, A. ; Hodel, U. ; Hsiang-Jen Huang ; Shih-Fen Huang ; Yimin Huang ; Kaltalioglu, E. ; Knoblinger, G. ; Ming-Tsan Lee ; Leslie, A. ; Pak Leung
Author_Institution :
Infineon Technol. Corp., Hopewell Junction, NY, USA
Abstract :
Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.
Keywords :
CMOS integrated circuits; SRAM chips; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; leakage currents; low-power electronics; mixed analogue-digital integrated circuits; permittivity; 0.25 micron; 1.5 V; 100 nm; 16 angstrom; 24 angstrom; 52 angstrom; CMOS technology; SRAM cell footprint; high performance components; low leakage components; low leakage gate-dielectric; low voltage operation; low-k BEOL; mixed-signal components; simultaneous single chip integration; triple-gate-oxide process; Artificial intelligence; CMOS technology; Capacitance; Capacitors; Dielectric substrates; Etching; Low voltage; Microelectronics; Radio frequency; Signal processing;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015388
