Thermal aware modern VLSI floorplanning

In this work, we present a Genetic (GA) algorithm based thermal-aware floorplanning framework. The primary objective for floorplanning is to minimize the total area required to accommodate all of the functional blocks on a chip and also to reduce high temperature and to distribute temperature evenly across a chip in an framework. B*tree representations with Genetic (GA) algorithm is used to calculate floorplanning temperature based on the power dissipation. The hotspot tool is used to reduce the high temperature and the algorithm is used to remove the dead space area. Area and/or temperature optimizations guide the GA algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.