A New Submicron MOSFET Technology with Gate Overlap on Twin Oxide (GOTO) LDD Structure

We propose a new self-aligned ITLDD process with minimum gate-drain overlap capacitance by employing a double stepped gate oxide under the overlapped gate and present our device and circuit simulation results to confirm the merits of the proposed gate-drain overlapped structures with respect to reliability and device performance by employing 2-D and 3-D device simulators.