Fast VLSI implementations for MRF and ANN applications

Author

Karathanasis, Haralambos C. ; Vlontzos, John A.

Author_Institution

INTRACOM S.A., Peania Attika, Greece

fYear

1993

fDate

6-9 Sep 1993

Firstpage

460

Lastpage

469

Abstract

A VLSI architecture for real-time Markov random field optimization is presented. This architecture contains a simple and fast hardware module implementing the sigmoid function using look-up tables and piecewise linear interpolation. Error bounds are given for computing with this module, and it is shown that it can also used for improving the performance of a systolic architecture for artificial neural network (ANN) implementations. Simulation results are presented

Keywords

Markov processes; VLSI; interpolation; neural chips; optimisation; piecewise-linear techniques; systolic arrays; table lookup; VLSI architecture; artificial neural network; error bounds; look-up tables; piecewise linear interpolation; real-time Markov random field optimization; sigmoid function; systolic architecture; Application software; Artificial neural networks; Computational modeling; Computer architecture; Electronic mail; Hardware; Interpolation; Piecewise linear techniques; Probability distribution; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks for Processing [1993] III. Proceedings of the 1993 IEEE-SP Workshop

Conference_Location

Linthicum Heights, MD

Print_ISBN

0-7803-0928-6

Type

conf

DOI

10.1109/NNSP.1993.471842

Filename

471842

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1908716