DocumentCode
1908732
Title
Polynomial-metamodel assisted fast power optimization of Nano-CMOS PLL components
Author
Mohanty, Saraju P. ; Kougianos, Elias ; Garitselov, Oleg ; Molina, Javier Moreno
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of North Texas, Denton, TX, USA
fYear
2012
fDate
18-20 Sept. 2012
Firstpage
233
Lastpage
238
Abstract
As the complexity of mixed-signal systems grows, the challenges of their design becomes exponentially more difficult. In order to mitigate this problem, this paper proposes a two stage approach that uses accurate metamodels and efficient algorithms for fast mixed-signal system optimization. The different components of a Phase-Locked Loop (PLL) are considered as case study. First, the metamodel creation process is presented. A simulated annealing based optimization algorithms then introduced for power optimization of the components. It is shown that the metamodel approach speeds up the optimization phase by 2000× with very good accuracy. The power consumption of the circuits is decreased by 22% for the baseline design and is within 8% of the circuit netlist-based, but computationally expensive approach.
Keywords
CMOS integrated circuits; mixed analogue-digital integrated circuits; phase locked loops; simulated annealing; baseline design; circuit netlist; fast mixed-signal system optimization; nano-CMOS PLL components; phase-locked loop; polynomial-metamodel assisted fast power optimization; simulated annealing based optimization algorithm; Accuracy; Integrated circuit modeling; Metamodeling; Phase locked loops; Polynomials; Simulated annealing; Fast Optimization; Metamodeling; Mixed-Signal Circuit Design; Nano-CMOS;
fLanguage
English
Publisher
ieee
Conference_Titel
Specification and Design Languages (FDL), 2012 Forum on
Conference_Location
Vienna
ISSN
1636-9874
Print_ISBN
978-1-4673-1240-0
Type
conf
Filename
6337017
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