Title :
Advanced 0.25-0.18 μm fully-planarized 6-level-interconnect CMOS technology for foundry manufacturing
Author :
Lin, T. ; Chen, C. ; Hsu, S.Y. ; Tsai, M.J. ; Yew, T.R. ; Chou, J.W. ; Huang, K.T. ; Wu, J.Y. ; Ku, Y.C. ; Liu, C.C. ; Yang, M.S. ; Yeh, W.K. ; Huang, C.H. ; Lur, W. ; Huang, H.S. ; Sun, S.W.
Author_Institution :
Tech. Dev. Div, United Microelectron. Corp., Hsin-Chu, Taiwan
Abstract :
An advanced 0.25-0.18 μm CMOS technology with fully-planarized 6-level-interconnect has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 μm layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. High performance devices with a dual-oxide (65/50 A) approach were developed for 3.3/2.5 V I/O and core circuits on the same chip. In addition, 0.18 μm, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 ps at 2.5 V for the 0.25 μm device, and 35 ps at 1.8 V for the 0.18 μm device. The embedded 6T SRAM cell size is 6.34 μm2. Considerations in process architecture and device design for foundry manufacturing are also addressed on this 6-level-metal 0.25-0.18 μm CMOS technology
Keywords :
CMOS integrated circuits; ULSI; integrated circuit design; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit technology; low-power electronics; surface treatment; 0.18 to 0.25 micron; 1.8 V; 2.5 V; 3.5 V; 6-level-interconnect CMOS technology; deep submicron technology; dual-oxide approach; embedded 6T SRAM cell; foundry manufacturing; fully-planarized CMOS technology; process architecture; CMOS process; CMOS technology; Contact resistance; Copper; Delay; Dielectrics; Foundries; Integrated circuit interconnections; Planarization; Tin;
Conference_Titel :
Semiconductor Manufacturing Technology Workshop, 1998
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-5179-7
DOI :
10.1109/SMTW.1998.722651
