An empirical study of etching for the fabrication of nanoscale imprinters

One of the greatest challenges facing nanotechnology is the ability to selectively place nanoscale entities in specific locations and subsequently interconnect these devices. Several methods have been proposed and the relative strengths of each technique will become apparent in time. One method that has received considerable attention in recent years is nanoimprint or nanostamp lithography. These techniques have shown resolution down to 10 nm, can be applied over large areas, are relatively inexpensive, and have several variations to accommodate different processing tasks. One common challenge in nanoimprint or nanostamp lithography is the fabrication of the imprinter or stamp. The features on the imprinter are usually fabricated using e-beam lithography and then etched. The etching step is often the determining factor in the quality of the imprinter. We have evaluated etching of 50 nm and 250 nm features in silicon and silicon dioxide using 16 different etching recipes. The features have been etched down approximately 200 nm resulting in an aspect ratio of 4 to 1 for the 50 nm features. The primary evaluation criteria is the anisotropy of the etch with the goal of achieving vertical sidewalls. In this paper, we present the 16 different etching recipes, the chamber conditions for three different reactors, and qualitative evaluations based upon SEM micrographs of each etch. For this work, we will concentrate on the nanoscale etching of SiO ₂. Several etching recipes are shown to be able to produce near-vertical walls for 50 nm features etched down 200 nm