Reduction of the Latch Effect in SOI MOSFETs by the Silicidation of the Source

A simple physical model is developed to assess the effect on single transistor latch voltage of carrier lifetime reduction and emitter efficiency degradation. The model predicts the efficacy of the latter mechanism and this is achieved experimentally by silicidation of the source. This has the effect of effectively placing the source ohmic contact close to the source/body metallurgical junction thus enhacing the hole component of the total current across the junction thereby reducing the emitter efficiency. In comparison to a non-silicided source, a 20% increase in breakdown voltage is achieved. Silicidation of both the source and drain regions is performed simultaneoulsy thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage current was observed.