Compact SPICE modeling and design optimization of low leakage a-Si:H TFTs for large-area imaging systems

We present a SPICE model that takes into account the different mechanisms underlying the reverse leakage current in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The main source of leakage current in these devices appears to be the parasitic reverse-biased p-i-n diode at the vicinity of the drain. At low gate voltages, the diode´s reverse current can be attributed to thermal generation of electrons from the valence to conduction bands through mid-gap states in the a-Si:H. At high gate voltages, the reverse current is due to trap-assisted tunneling, whereby electrons tunnel to the conduction band through mid-gap states. This bias dependent behavior has been modeled and implemented in SPICE using simple circuit elements based on voltage controlled current sources. Simulated and measured reverse leakage current characteristics are in reasonable agreement