Process window study of the stacked via structure in dual-damascene process

Author

Saitoh, Takaki ; Wada, Hideyuki ; Kitamura, Kohji

Author_Institution

Dept. of Semicond. Oper., IBM Japan Ltd., Shiga, Japan

fYear

1997

fDate

6-8 Oct 1997

Abstract

The stacked via structure in dual-damascene process is one of the best ways to shrink the chip size and minimize the process steps for the cost reduction. In this report, the photolithography process window of the stacked via structure is examined using positive resist with the dye by i-line stepper. The reverse damascene process is developed for achieving enough photolithography process window

Keywords

VLSI; application specific integrated circuits; photoresists; chip size; cost reduction; dual-damascene process; i-line stepper; photolithography process window; positive resist; process steps; reverse damascene process; stacked via structure; Absorption; Application specific integrated circuits; Coatings; Costs; Lithography; Logic; Random access memory; Resists; Shape; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-3752-2

Type

conf

DOI

10.1109/ISSM.1997.664603

Filename

664603

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1909051