A ferroelectric analog associative memory technology employing hetero-gate floating-gate-MOS structure

Author

Kobayashi, D. ; Shibata, T. ; Fujimori, Y. ; Nakamura, T. ; Takasu, H.

Author_Institution

Dept. of Frontier Informatics, Univ. of Tokyo, Japan

fYear

2002

fDate

11-13 June 2002

Firstpage

116

Lastpage

117

Abstract

An analog associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the associative memory cell to a wide voltage range of the input signal, a hetero-gate floating-gate-MOS structure has been introduced. The concept has been experimentally verified using fabricated test devices and circuits.

Keywords

MIS structures; analogue storage; content-addressable storage; dielectric depolarisation; dielectric hysteresis; ferroelectric storage; lead compounds; leakage currents; PZT; PZT process; PbZrO3TiO3; associative memory cell; depolarization; ferroelectric analog associative memory technology; hetero-gate floating-gate-MOS structure; hysteresis loops; maximum likelihood vector; read-out voltage; template vector information storage; wide voltage range; Associative memory; Circuit testing; Ferroelectric materials; Informatics; MOS capacitors; Nonvolatile memory; Polarization; Research and development; Switches; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015415

Filename

1015415