Title :
60 nm gate length dual-Vt CMOS for high performance applications
Author :
Mehrotra, M. ; Wu, J. ; Jain, A. ; Laaksonen, T. ; Kim, K. ; Bather, W. ; Koshy, R. ; Chen, J. ; Jacobs, J. ; Ukraintsev, V. ; Olsen, L. ; Deloach, J. ; Mehigan, J. ; Agarwal, R. ; Walsh, S. ; Sekel, D. ; Tsung, L. ; Vaidyanathan, M. ; Trentman, B. ; Liu,
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series resistance by reduction of dopant loss and higher dopant activation, resulting in n- and pMOS I/sub drive/ of 1160 /spl mu/A//spl mu/m and 550 /spl mu/A//spl mu/m at 1.3 V at I/sub off/=100 nA//spl mu/m.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit technology; ion implantation; low-power electronics; nitridation; plasma materials processing; ultraviolet lithography; 0.13 micron; 1.3 V; 1.75 nm; 193 nm; 193 nm gate lithography; 60 nm; 60 nm gate length dual-Vt CMOS; EOT; L-shaped nitride spacer; MOSFET; dopant activation; dopant loss reduction; drain extension implant; drive current; dual spacers; dual threshold voltage; high performance applications; nMOS; pMOSFET; remote-plasma nitrided dielectric; series resistance; thin spacer; Annealing; CMOS process; CMOS technology; Capacitance; Degradation; Implants; MOS devices; Silicon; Space technology; Temperature;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015419
