Enhanced power gating schemes for low leakage low ground bounce noise in deep submicron circuits

Design of complex arithmetic logic circuits considering ground bounce noise, noise immunity, leakage current, active power and area is an important and challenging task in deep submicron circuits. In this paper, a comparative analysis of high performance stacking power gating schemes is done which minimizes the leakage power and provides a way to control the ground bounce noise. The innovative power gating schemes such as stacking power gating, diode based stacking power gating are analyzed which minimizes the peak of ground bounce noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 87.14% over the conventional power gating. It is also found that in stacking power gating, the ground bounce noise has been reduced by 76.28% over the conventional power gating scheme. We have performed simulations using Cadence-Spectre in a 90nm standard CMOS technology at room temperature with supply voltage of 1V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective roadmap for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.