Gate postdoping to decouple implant/anneal for gate, source/drain, and extension: maximizing polysilicon gate activation for 0.1 /spl mu/m CMOS technologies

We present a systematic study on maximizing polysilicon gate activation for aggressively scaled 0.1 /spl mu/m CMOS technologies. The fundamental limit of gate activation due to poly depletion effect was investigated in terms of gate implant/anneal condition and sequence, poly grain size, dopant penetration and activation. For the first time, we achieved significant improvement in CMOS performance by developing a novel process of "gate postdoping" to decouple implant and anneals for gate, source/drain, and extension. The method successfully reduces the poly depletion effect and thus the equivalent gate oxide thickness in inversion by up to /spl sim/2 /spl Aring/, improving CMOS on-currents by 9/spl sim/33% over a conventional process.