A 3.52 GSps throughput VLSI architecture of I/Q imbalance compensator for 60 GHz communication system

This paper presents an I/Q imbalance compensator which can support the throughput rate of 3.52 GSps and improve the signal-to-interference ratio (SIR) from 10.1 dB to 33 dB for a 60-GHz communication system in the IEEE 802.11ad standard. The equivariant adaptive separation via independence (EASI) algorithm is adopted. This blind-source separation (BSS) approach requires no prior information and demands no training sequence. To reduce its complexity, the equation to update the separating matrix is simplified. Furthermore, to achieve the target throughput, a 16-parallel signal processing structure unfolded from the corresponding serial structure which directly implements the simplified algorithm is adopted. Moreover, two modifications including the relaxed look-ahead computation and the slowing down of matrix updating are applied to increase the processing speed and decrease the hardware cost for VLSI implementation. Finally, the whole structure is implemented using Silterra 0.13 um process with a core area of 0.36 mm².