ASIC implementation of frequency domain equalizer for single carrier transmission

Since single-carrier (SC) transmission using frequency domain equalization (FDE) with minimum mean square error (MMSE) operates at lower peak-to-average power ratio (PAPR) than orthogonal frequency division multiplexing (OFDM), SC-FDE with MMSE is a main candidate for uplink of cellular system such as long term evolution (LTE). In this paper, an application specific integrated circuit (ASIC) chip for the SC-FDE is implemented on Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal-oxide semiconductor (CMOS). The chip size is 5.86 mm². The power consumption is 200 mW at data rate of 4.86 Mbit/s. In the condition of 16 paths uniform power delay profile, at a bit error rate (BER) of 10^-4, the degradation of measured E_b/N₀ from computer simulation is found to be less than 1 dB.