DocumentCode
1909963
Title
Rational clocking [digital systems design]
Author
Sarmenta, Luis F G ; Pratt, Gill A. ; Ward, Stephen A.
Author_Institution
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
271
Lastpage
278
Abstract
Communication between independently-clocked digital subsystems typically involves a finite probability of synchronization failure whose minimization introduces delays and consequent performance costs. This paper explores a technique that eliminates both the inherent unreliability of such communication and the performance overhead it implies. Our approach maintains a known phase relationship, between clocks whose frequencies are related by a rational factor, and exploits the predictability of their relative phases to algorithmically time communications without run-time arbitration contests
Keywords
clocks; delays; logic design; minimisation of switching nets; synchronisation; delays; digital systems design; finite probability; independently-clocked digital subsystems; logic design; phase relationship; rational clocking; synchronization failure; Clocks; Computer science; Control systems; Counting circuits; Delay; Frequency synchronization; Laboratories; Phase locked loops; Table lookup; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7165-3
Type
conf
DOI
10.1109/ICCD.1995.528821
Filename
528821
Link To Document