Title :
Lithography solution for 65-nm node system LSIs
Author :
Matsuo, T. ; Endo, M. ; Kishimura, S. ; Misaka, A. ; Sasago, M.
Author_Institution :
ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
Abstract :
For 65-nm node devices, we have systematically investigated the lithographic margin of electron-beam projection lithography (EPL), ArF lithography and vacuum ultraviolet (VUV) lithography. Among them, EPL has sufficient margin and excellent pattern fidelity and our experiments have demonstrated that it can fabricate 65-nm node device patterns. Therefore, EPL is a strong candidate for 65-nm node lithography.
Keywords :
VLSI; electron beam lithography; integrated circuit technology; ultraviolet lithography; 65 nm; 65-nm node system LSIs; ArF lithography; electron-beam projection lithography; lithographic margin; pattern fidelity; vacuum ultraviolet lithography; Fabrication; Large scale integration; Lithography; Logic gates; Optical attenuators; Page description languages; Resists; Ultraviolet sources; Vacuum systems; Vacuum technology;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015450
