Square-Octagon interconnection architecture for Network-on-chips

The importance of Network-on-chips has been sharply increased during the past few years. The credit goes to the ability of increasing a large number of cores on a single chip. Consequently, a number of research studies have been done to cope with the challenges that face the on-chip networks such as: providing high-performance (low-latency and high-bandwidth), simplicity, flexibility, scalability, power efficiency. This paper proposes a new on-chip communication architecture called Square-Octagon NoC Architecture (SONoC), which can meet the performance requirement of multiprocessor system-on-chip (SoC). The SONoC architecture provides higher bandwidth that increases rapidly with the increasing of the network scale and a lower latency due to the diagonal links in between. The paper introduces the topology and a developed routing algorithm, and finally demonstrates the performance with the results obtained from simulations. Simulation is carried out and compared with 2D Mesh, which is the most frequently used topology for NoC due to its scalability, symmetry, simplicity and high regularity.