An efficient test design for CMPs cache coherence

This work proposes an efficient test design for verification of cache coherence in CMPs (Chip Multiprocessors). It ensures data coherence more accurate and reliable in a system with thousands of on-chip processors. The design is based on the theory of a special class of Cellular Automata (CA) referred to as the SACA and can effectively be exploited to realize the conventional MSI/MESI/MOESI protocols. The SACA realizes quick identification of the inconsistencies in cache line states of processors´ private caches. The simple hardware realization of CA architecture enables low cost VLSI implementation of the verification logic.