Fully parallel and fully serial architecture for realization of high speed FIR filters with FPGA´s

This paper presents fully parallel and fully serial architectures for Band pass filter. The performances of fully parallel and fully-serial architectures are analyzed for different quantized versions of representation. Filters generated using 8 bit fixed point implementation requires smaller area usage when compared to 16 bit fixed point implementation at the cost of imprecision. The proposed implementations are synthesized with Xilinx ISE 13.2 version. Family of device was Spartan 3E and target device was xa3s250e-4vqg100. The key performance metrics, namely number of Slices, Slice Flip Flops, LUTs, Maximum frequency are compared.