A complementary GaAs PLL clock multiplier with wide-bandwidth and low-voltage operation

This paper reports a phase-locked loop clock multiplier designed for wide-bandwidth operation at supply voltages of 0.9 V to 1.5 V. Implemented in Motorola´s complementary GaAs (CGaAs/sup TM/) process, the target application is the PUMA processor, a multi-chip microprocessor based on the PowerPC instruction set architecture. This system operates on an input system clock of 100-125 MHz, while the processor clock is targeted to run at a frequency of 1 GHz. Phase-locked loop clock multiplication factors of 2 to 16 are supported, while the achievable output frequency ranges from 110 MHz to 775 MHz. The chip utilizes Motorola´s 0.7 /spl mu/m CGaAs/sup TM/ process and is entirely implemented with the direct-coupled FET standard cell library developed for the PUMA project. This paper discusses the design and implementation of the clock multiplier. Test results are presented. The design measures 1.4 mm/sub 2/, including the fully integrated passive filter. The core power dissipation is 300 mW at 1.5 V, and 36 mW at 0.9 V.