Concurrent automatic test pattern generation algorithm for combinational circuits

The test generation problem for combinational circuits is known to be NP-hard. Efficient techniques for test generation are essential in order to reduce the test generation time. In this paper, we present a new and efficient test generation system based on global computations techniques. We aim at reducing the test generation time by using concurrent search to find tests for more than one fault at a time as opposed to the single target fault technique used by current test systems. In order to achieve our objective, a new, model for test generation is presented. We present a formal definition for the new test generation model and an implementation for the test generation system. Experimental results using ISCAS´85 and ISCAS´89 benchmarks are also presented