DocumentCode
1910465
Title
A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide
Author
Suzuki, A. ; Tabuchi, K. ; Kimura, Hiromitsu ; Hasegawa, T. ; Kadomura, S.
Author_Institution
LSI Technol. Dev. Group, Sony Corp., Kanagawa, Japan
fYear
2002
fDate
11-13 June 2002
Firstpage
216
Lastpage
217
Abstract
This paper is a report on the effect of processing to form interconnects by using copper and a material with a low dielectric constant (copper/low-k) on the negative-bias temperature instability (NBTI) of p-MOSFETs. We found that the NBT-stress lifetime of copper/low-k interconnects is shorter than that of aluminum/SiO/sub 2/ interconnects. The NBTI strongly depends on the cap layer over the copper/low-k layer, on the intermetal dielectric (IMD) film, on the barrier-metal film, and on the temperature of post-metal annealing (PMA). Based on these results, we developed methods for reducing the NBTI in next-generation MOSFETs.
Keywords
MOSFET; annealing; copper; dielectric thin films; semiconductor device metallisation; semiconductor device reliability; Cu; NBT-stress lifetime; barrier-metal film; cap layer; copper/low-k BEOL process; interconnects; intermetal dielectric; negative-bias temperature instability; p-MOSFETs; post-metal annealing; ultra-thin gate oxide; Aluminum; Annealing; Copper; Dielectric constant; Dielectric films; Dielectric materials; MOSFET circuits; Niobium compounds; Temperature dependence; Titanium compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7312-X
Type
conf
DOI
10.1109/VLSIT.2002.1015458
Filename
1015458
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