DocumentCode :
1910466
Title :
An HVD based error detection and correction of soft errors in semiconductor memories used for space applications
Author :
Sharma, Shalini ; Vijayakumar, P.
Author_Institution :
Dept. of Electron. & Commun., SRM Univ., Chennai, India
fYear :
2012
fDate :
15-16 March 2012
Firstpage :
563
Lastpage :
567
Abstract :
Exposure to electromagnetic radiations (high speed a ray particles) is a prominent problem in all the semiconductor memories of on-board computing unit used for space application. So, in this paper, an error detection and correction method to protect the semiconductor memories against the soft errors is proposed. This method is based on 2-d parities. The parity bits are calculated at the receiver end for each row, column and diagonal in slash and backslash directions in a memory array. The parities are regenerated at the receiver end; the comparison of transmitted and received parity bits detects the error. As soon as the error is detected, the code corrects the detected error. Hamming code is used for error detection and correction. It uses parity codes in each of the four directions (that are horizontal, vertical, forward slash diagonal and backslash diagonal) in a data part. Correction code can correct an error in each row, column, and forward slash diagonal and back slash diagonal. This method is implemented on an FPGA device and it is evaluated for an on-chip RAM of a Virtex device. This method is a promising technique to detect and correct errors in semiconductor memories in presence of large electromagnetic interference and hazards with less computational complexity.
Keywords :
Hamming codes; SRAM chips; computational complexity; electromagnetic interference; error correction codes; error detection codes; field programmable gate arrays; hazards; space vehicle electronics; 2D parity codes; HVD based error detection method; Hamming code; SRAM-based FPGA; Virtex device; back slash diagonal; computational complexity; electromagnetic interference; electromagnetic radiation; error correction code device; forward slash diagonal; hazards; horizontal-vertical- diagonal method; memory array; on-board computing unit; on-chip RAM; received parity bits; receiver end; semiconductor memories; soft error correction method; transmitted parity bits; Hardware; Logic gates; Multiplexing; Random access memory; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Devices, Circuits and Systems (ICDCS), 2012 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4577-1545-7
Type :
conf
DOI :
10.1109/ICDCSyst.2012.6188771
Filename :
6188771
Link To Document :
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