Partitioning in 3D ICs: A TSV aware strategy with area balancing

3D ICs offer an attractive alternative to 2D planar ICs. They provide increased system integration by either increasing functionality or combining different technologies. Using 3D ICs allows for integrating the best technology for a particular portion of an application into the chip cube. For 3D designs to achieve their full potential, it is necessary to devise appropriate physical design strategies that can handle the complexities and new objectives specific to 3D design. Netlist partitioning is an important part of the physical design strategy that partitions the entire netlist into multiple partitions to be assigned to multiple tiers during design. Although there are research works concerned with placement and routing in 3D ICs, not a great deal of research work addressed this particular phase of physical design strategy. This work proposes a netlist partitioning strategy to partition the entire netlist into a number of tiers while considering minimization of inter-tier interconnection as well as area balancing. The novelty of this strategy is that even considering 1000 logic modules, the variation of the area between different tiers does not exceed 0.46% and the number of inter-tier interconnections is also within 27. Minimization of the number of inter-tier interconnections leads to minimization of area as well since the inter-tier interconnections are implemented using Through-Silicon Vias (TSV) which consume a lot of area.