FPGA implementation of AES algorithm using Composite Field Arithmetic

A Low area Advanced Encryption Standard (AES)-128 bit algorithm is proposed in this paper. This technique is implemented using Composite Field Arithmetic (CFA) in byte substitution block, inverse byte substitution block and key expansion block of AES algorithm. The Composite field arithmetic technique provides a low area than the Look Up Table (LUT) in S-Box/Inverse S-Box. The proposed technique is presented with multistage sub-pipelined architecture in order to increase the throughput and its performance is compared with the previous FPGA implementations.