Analysis and modeling of 1/f noise in mosfets: The joint effect of channel length and channel resistance

Semiconductor devices possess some resistance in their channel or conducting slab (channel) which is a powerful source of 1/f noise. The 1/f noise in MOSFET is to be created by bias voltage applied to the device. In this paper the analysis of results are carried out on MOS transistors in 0.35, 0.25 and 0.18 μm technologies available from TSMC foundry. Comparison of power spectrum density of 1/f noise has been made for different channel lengths in NMOSFET and PMOSFET. Dependency of bias voltage on 1/f noise in MOSFETs has been investigated. It is reported from simulation results that gate oxide thickness and channel doping concentration can be varied for the reduction of 1/f noise. Based upon 1/f resistance noise due to channel length, a two stage common source amplifier is designed in 0.18 μm technology and analysis of 1/f noise is carried out to find voltage noise density as 29.56nV/√Hz(1KHz), 9.73nV/√Hz (10KHz), 3.01nV/√Hz (1MHz).