High-speed and low-power ASIC implementation of OFDM transceiver based on WLAN (IEEE 802.11a)

In this paper, we present the ASIC Implementation of OFDM transceiver based on WLAN (IEEE 802.11a) for better optimized power and timing. RTL synthesis of transmitter and receiver blocks without (Viterbi) decoder in the receiver is presented here. While the Punctured Convolution Coding is used to improve the data rate, Quadrature Amplitude modulation improves bandwidth. OFDM is implemented using FFT/IFFT processor. Using separate clocks for modulator/demodulator and transmitter/receiver improves data rate. Timing constraints are met by introducing retiming and Clock Scheduling. Multi-V_TH principles and Clock gating are applied to reduce power consumption. The proposed design has been implemented in TSMC 0.18 μm technology. The total area of the chip occupied 2.4×2.4 mm² and the dynamic power consumption is 72mW, data rate at 91Mbps and 1.8V supply voltage. Our ASIC achieves a considerable performance gain as well support about double data rate as compared to the conventional IEEE 802.11a WLANs.