Title :
Performance evaluation of Junctionless Vertical Double Gate MOSFET
Author :
Rahul, Jagdeep ; Srivastava, Anurag ; Yadav, Shekhar ; Jha, Kamal Kishor
Author_Institution :
VLSI Design Lab., ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior, India
Abstract :
In this paper, we present a comparative analysis of Junctionless Vertical Double Gate MOSFET (JLVMOS) with conventional Junction Vertical Double Gate MOSFET (JVMOS) by using TCAD Tool simulations. In our observations drain induced barrier lowering (DIBL), Subthreshold Swing (S. Swing) and leakage current (IOFF) are found to be reduced than those of its respective junction VMOS counterparts, hence the Junctionless VMOS gets same drive current based on same VGS as compared to the Junction VMOS and its short-channel characteristics get improved.
Keywords :
MOSFET; leakage currents; semiconductor device models; JLVMOS; TCAD Tool simulations; drain induced barrier lowering; junctionless vertical double gate MOSFET; leakage current; performance evaluation; subthreshold swing; CMOS integrated circuits; Logic gates; Substrates; DIBL; Junction Vertical Double Gate MOSFET (JVMOS); Junctionless Vertical Double Gate MOSFET (JLVMOS); Subthreshold Swing; TCAD Tool; leakage current (IOFF);
Conference_Titel :
Devices, Circuits and Systems (ICDCS), 2012 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4577-1545-7
DOI :
10.1109/ICDCSyst.2012.6188796
