DocumentCode
1911638
Title
A dynamic cache sub-block design to reduce false sharing
Author
Kadiyala, Murali ; Bhuyan, Laxmi N.
Author_Institution
Nat. Instrum. Corp., Austin, TX, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
313
Lastpage
318
Abstract
Parallel applications differ from significant bus traffic due to the transfer of shared data. Large block sizes exploit locality and decrease the effective memory access time. It also has a tendency to group data together even though only a part of it is needed by any one processor. This is known as the false sharing problem. This research presents a dynamic sub-block coherence protocol which minimizes false sharing by trying to dynamically locate the point of false reference. Sharing traffic is minimized by maintaining coherence on smaller blocks (sub-blocks) which are truly shared, whereas larger blocks are used as the basic units of transfer. Larger blocks exploit locality while coherence is maintained on sub-blocks which minimize bus traffic due to shared misses. The simulation results indicate that the dynamic sub-block protocol reduces the false sharing misses by 20 to 30 percent over the fixed sub-block scheme
Keywords
cache storage; memory architecture; memory protocols; bus traffic; dynamic cache sub-block design; dynamic sub-block coherence protocol; false sharing; simulation results; Access protocols; Application software; Bridges; Computer science; Counting circuits; Delay; Hardware; Instruments; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7165-3
Type
conf
DOI
10.1109/ICCD.1995.528827
Filename
528827
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