Title :
Memory-intensive benchmarks: IRAM vs. cache-based machines
Author :
Gaeke, B.R. ; Husbands, P. ; Li, X.S. ; Oliker, L. ; Yelick, K.A. ; Biswas, R.
Author_Institution :
Comput. Sci. Div., California Univ., Berkeley, CA, USA
Abstract :
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive benchmarks to evaluate a mixed logic and DRAM processor called VIRAM as a building block for scientific computing. For each benchmark, we explore the fundamental hardware requirements of the problem as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. Results indicate that VIRAM is significantly faster than conventional cache-based machines for problems that are truly limited by the memory system and that it has a significant power advantage across all the benchmarks.
Keywords :
DRAM chips; data structures; memory architecture; parallel processing; performance evaluation; DRAM processor; IRAM; VIRAM; architectural models; data structures; fine-grained parallelism; memory access; memory-intensive benchmarks; mixed logic; Application software; Arithmetic; Bandwidth; Computer architecture; Hardware; Parallel processing; Process design; Random access memory; Registers; Scientific computing;
Conference_Titel :
Parallel and Distributed Processing Symposium., Proceedings International, IPDPS 2002, Abstracts and CD-ROM
Conference_Location :
Ft. Lauderdale, FL
Print_ISBN :
0-7695-1573-8
DOI :
10.1109/IPDPS.2002.1015506