Effect of board design and assembly process on leakage currents of ceramic chip capacitors

Author

Chang, D.D. ; Anderson, F.R.

Author_Institution

AT&T Bell Lab., Princeton, NJ, USA

fYear

1990

fDate

20-23 May 1990

Firstpage

1035

Abstract

An experiment designed to study the effects of mounting pad configurations on the tendency toward thermal cracking and/or leakage currents of 1206 and 0805-size SMCs (surface-mounted ceramic chip capacitors) was conducted. The results show that, with the maximum delta temperature of 135°C, vias, traces, long pads, and heat sinks do not cause thermal cracking. No significant differences were found between SMCs mounted on FR-4 boards and FR-2 boards. The differences in capacitor dielectrics were insignificant, except that one particular capacitor designed with a thinner dielectric layer suffered more failures

Keywords

assembling; capacitors; packaging; surface mount technology; 135 degC; FR-2 boards; FR-4 boards; SMCs; assembly process; board design; capacitor dielectrics; ceramic chip capacitors; failures; heat sinks; leakage currents; maximum delta temperature; mounting pad configurations; thermal cracking; traces; vias; Assembly; Capacitors; Ceramics; Dielectrics; Leakage current; Process design; Sliding mode control; Surface cracks; Temperature; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1990. ., 40th

Conference_Location

Las Vegas, NV

Type

conf

DOI

10.1109/ECTC.1990.122314

Filename

122314