Analysis of Hot Carrier Induced Degradation in Polycrystalline Silicon Thin Film Transistors

In this work the hot carrier effects in polycrystalline thin-film transistors, mainly related to hot-holes, are analysed by using a two-dimensional device analysis program. The experimental results have been interpreted in terms of formation of trap centers in the gate oxide and interface states. Furthermore, the theoretical analysis of alternate stresses allowed the determination of the extension of the interface region (100 nm close to the drain junction) damaged by the hot-holes.