Title :
Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage
Author :
Katsumata, Y. ; Itoh, N. ; Nakajima, H. ; Inou, K. ; Iinuma, T. ; Matsuda, S. ; Yoshino, C. ; Tsuboi, Y. ; Iwai, H.
Author_Institution :
ULSI Labs., Toshiba Corp., Kawasaki, Japan
Abstract :
Reduction in parasitic capacitance and resistance is effective to improve ECL gate delay, as well as increase in fT values. In this paper, we demonstrate a device with sub-20 ps tpd values even at fT = 22 GHz by implementing several techniques to reduce parasitics. The relatively low fT of this design results in a high breakdown voltage of 5 V.
Keywords :
delays; electric breakdown; emitter-coupled logic; microwave bipolar transistors; ECL bipolar transistor technology; ECL gate delay; frequency 22 GHz; high breakdown voltage; parasitic capacitance reduction; parasitic resistance reduction; time 20 ps; tpd value; voltage 5 V; Bipolar transistors; Cutoff frequency; Delay effects; Etching; Germanium silicon alloys; Laboratories; Parasitic capacitance; Research and development; Silicon germanium; Ultra large scale integration;
Conference_Titel :
Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European
Conference_Location :
Grenoble
