Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes

The constant increase of subthreshold current of nanometer transistors due to technology scaling may hinder the evolution of high-performance chips in the near future. This evokes the need of accurate leakage power modeling for new nanometer technologies. In this paper, we present an improved subthreshold current model, which was integrated it into an architectural-level power simulator. Using this simulator, we estimated the leakage power in a 2 MB cache memory for 32 nm and 16 nm technology nodes. Our results show that the cache leakage power dissipation for 2 MB 2-way cache at 100°C fabricated in the 32 nm technology is around 1 W. For the 16 nm technology, we demonstrate the importance of maintaining high threshold voltage to keep leakage power density at the acceptable level.