A novel architecture for an ATM switch

Multicast function is essential for an ATM switch. We propose a novel architecture for an output-buffer ATM switch and a shared-buffer ATM switch to realize the multicast function in a more efficient way. In an output-buffer ATM switch, we dedicate a first-in and first-out (FIFO) shared buffer for all multicast cells to increase buffer utilization. In a shared-buffer ATM switch, we dedicate a FIFO address queue for all multicast cells to simplify the design of the control logic. Performance evaluation of the new switch is also provided. Since each multicast cell occupies only one buffer space, the proposed switch achieves a better cell-loss performance under multicast traffic loads without the need for complicated control circuitry