DocumentCode
1912722
Title
Split timing mode (STM)-answer to dual frequency domain testing
Author
Sivaram, A.T.
Author_Institution
Schlumberger Semicond. Solutions, San Jose, CA, USA
fYear
2001
fDate
2001
Firstpage
140
Lastpage
147
Abstract
This paper describes Split Timing Mode (STM), a dual timing domain ATE architecture, which allows selected channels to run at a different frequency from others. The paper also details the timing, pattern and datalogging details of STM, with examples to show how it can make it easier for the test engineer to develop and debug tests for these classes of devices
Keywords
automatic test equipment; automatic test pattern generation; automatic test software; integrated circuit testing; logic testing; timing; ATPG; STM pattern generation; datalogging; digital functional tests; dual frequency domain testing; dual time domain asynchronous buses; dual time domain synchronous buses; dual timing domain ATE architecture; split timing mode; test program; Clocks; Computer industry; Design engineering; Frequency domain analysis; Microcomputers; Microprocessors; Semiconductor device testing; Silicon; Switches; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2001. Proceedings. International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-7169-0
Type
conf
DOI
10.1109/TEST.2001.966627
Filename
966627
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