Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique

Author

Wu, Kaijie ; Karri, Ramesh

Author_Institution

Dept. of Electr. & Comput. Eng., Polytech. Univ. Brooklyn, NY, USA

fYear

2001

fDate

2001

Firstpage

221

Lastpage

229

Abstract

Proposes an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the register transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. We show that proposed scheme provides very good CED capability with very low area overhead

Keywords

VLSI; error detection; fault diagnosis; high level synthesis; redundancy; resource allocation; transient analysis; CED scheme; RT level; VLSI permanent faults; algorithm level recomputing; allocation diversity; area overhead; concurrent error detection technique; hardware allocation diversity; normal computation; operation-to-operator allocation; register transfer level time redundancy; transient faults; Adders; Bidirectional control; Circuit faults; Electrical fault detection; Error correction; Fault detection; Hardware; Logic; Redundancy; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966637

Filename

966637