Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip

System-on-a-chip (SoC) built with embedded IP cores offers attractive methodology design reuse, reconfigurability, and customizability. But integration of design-for-testability (DfT) structures of IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time-to-market by taking core test data from the design environment and automatically generating DfT structures that can be easily integrated into SoC. A novel automated synthesis methodology to generate SoC built-in self-test (BIST) in order to test IP and custom logic cores with high fault coverage is proposed. The proposed technique, modified configurable 2-D LFSR, is modeled after the principle of configurable 2-D LFSR design, which generates a deterministic sequence of test vectors for random-vector- resistant faults, and then random test vectors for random- vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2-D LFSR design by replacing the XOR gates used in the conventional LFSRs with simple logic gates like NOR and NAND. Moreover, the proposed approach is capable of optimizing 2-D LFSRs with consideration of don´t-care bits in incompletely specified test patterns.