Title :
New trends in microelectronics: Towards an ultimate memory concept
Author :
Makarov, A. ; Sverdlov, V. ; Selberherr, S.
Author_Institution :
Inst. for Microelectron., Tech. Univ. Wien, Vienna, Austria
Abstract :
Memory is an indispensible component of any modern integrated circuit. While MOSFET scaling has advanced tremendously, traditional DRAM cell scaling is hampered by the presence of a capacitor which is difficult to reduce in size. Recently, an interesting concept of a DRAM memory cell based on a transistor alone was introduced. The ultimate advantage of this new concept is that it does not require a capacitor, and, in contrast to traditional 1T/1C DRAM cells, it represents a 1T/0C cell named Z(for zero)-RAM. The advanced Z-RAM bitcells built on a multiple-gate MOSFET (MuGFET) utilizes the bipolar transistor usually considered as parasitic [1]. The advantage is that the current flows through the body of the structure. The majority carriers are generated by impact ionization and stored under the gates. The charge stored opens the bipolar transistor guaranteeing high current (state 1). The stored charge can be flashed out by applying the voltage pulse to the gates returning the bipolar transistor into the low current state 0. The stored charge for the bipolar transistor in the high current and low current states is shown in Fig.1. The results [2] of current calculations as function of the gate voltage for a double-gate structure with 10nm thin body are shown in Fig.2. In a forward scan direction of the gate voltage, the current stays low until a certain critical value is reached. After that the source-drain current rapidly increases by several orders of magnitude. In a reverse gate voltage scan, the current first slowly decreases, however, due to the charge stored under the gates, the relatively large current value is maintained down to the negative gate voltages, where it abruptly decreases by several orders of magnitude completing the hysteresis loop [2]. The use of vertical gate-all around transistors extends the Z-RAM roadmap to future generations. One disadvantage of the Z-RAM cell is the relatively high operating voltage needed to ignite impact ionization. To red- ce the operating voltage, a new concept of a 1T/0C cell was recently proposed [3].
Keywords :
DRAM chips; MOSFET circuits; bipolar transistor circuits; capacitors; hysteresis; integrated circuits; DRAM cell scaling; MOSFET scaling; MuGFET; Z-RAM roadmap; bipolar transistor; capacitor; hysteresis loop; integrated circuit; microelectronics; multiple-gate MOSFET; ultimate memory concept; Bipolar transistors; Logic gates; Magnetic domains; Magnetic hysteresis; Magnetic switching; Random access memory; Switches;
Conference_Titel :
Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on
Conference_Location :
Playa del Carmen
Print_ISBN :
978-1-4577-1116-9
Electronic_ISBN :
978-1-4577-1115-2
DOI :
10.1109/ICCDCS.2012.6188887