Title :
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Author :
Bartenstein, Thomas ; Heaberlin, Douglas ; Huisman, Leendert ; Sliwinski, David
Abstract :
A new way of diagnosing ICs that fail logic tests is described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults
Keywords :
automatic testing; combinational circuits; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; SLAT-based diagnosis; bridges; combinational logic designs; defect model; fault. diagnosis; logic ICs; logic tests; multi-pin defects; single location at-a-time paradigm; test pattern application; Circuit faults; Circuit testing; Integrated circuit testing; Logic design; Logic testing; Microelectronics; Pattern matching; Pins; Process design; Robustness;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966644
