Title :
Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement
Author :
Khalil, MohammadAthar ; Wey, Chin-Long
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
Extreme-voltage screening has been successfully implemented to enhance gate-oxide reliability of digital CMOS ICs. However, the success has not yet been extended to its analog counterparts. As a result, almost all the manufacturers employ the digital circuit screening process for the analog modules in mixed-signal CMOS ICs. Our pervious study had addressed the issues on how to properly stress analog circuits to enhance the gate-oxide reliability of mixed-signal CMOS integrated circuits, and the trade-off between the stress coverage and stress time. This paper presents two algorithms that generate a set of stress vectors for an analog circuit (1) to meet the stress coverage requirement and to result in a minimum stress time; and (2) to meet the stress time requirement and to result in a maximum stress coverage
Keywords :
CMOS analogue integrated circuits; VLSI; failure analysis; integrated circuit reliability; integrated circuit testing; mixed analogue-digital integrated circuits; production testing; IC manufacture; VLSI devices; analog CMOS ICs; extreme-voltage screening; extreme-voltage stress vector generation; gate-oxide reliability enhancement; maximum stress coverage; minimum stress time; mixed-signal CMOS integrated circuits; mixed-signal IC; stress coverage requirement; stress testing; stress time requirement; Analog circuits; CMOS process; Circuit testing; Costs; Degradation; Integrated circuit testing; Manufacturing processes; Plasma devices; Plasma materials processing; Stress;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966651
