Testing beyond EPA: TDF methodology solutions matrix

Author

Jain, Sunil K. ; Chema, Greg P.

fYear

2001

fDate

2001

Firstpage

424

Lastpage

432

Abstract

Accurate detection and fast resolution of device measurement is one of the most intriguing test challenges now and in the foreseeable future. This is especially true for those devices with input/output (IO) speeds and electrical characteristics which exceed the automatic test equipment (ATE) edge placement accuracy (EPA) and/or overall tester accuracy (OTA). The tester derating factor (TDF) methodology described in this paper is an evolving solutions matrix being used by the Intel Chipset Engineering Group to turn this challenge into a competitive advantage. This paper describes how the TDF matrix can help engineers take full advantage of existing equipment, including testing devices beyond the vendor specified/published EPA/OTA, and suggests ways for the ATE vendors to partner with users to enable this capability on existing/future testers

Keywords

automatic test equipment; calibration; high-speed integrated circuits; integrated circuit testing; ATE; ATE EPA; ATE calibration; ATE edge placement accuracy; EPA testing; TDF matrix; TDF methodology solutions matrix; accurate detection; automatic test equipment edge placement accuracy; device electrical characteristics; device input/output speeds; device measurement resolution; device testing; high-speed device validation; overall tester accuracy; test measurement accuracy; tester derating factor methodology; Automatic test equipment; Automatic testing; Benchmark testing; Calibration; Electric variables; Equations; Hardware; Jitter; Measurement errors; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966659

Filename

966659