Title :
Test methodology for the McKinley processor
Author :
Josephson, Don Douglas ; Poehlman, Steve ; Govan, Vincent ; Mumford, Clint
Author_Institution :
Hewlett-Packard Co., USA
Abstract :
The McKinley processor is the result of a joint design effort between Intel and Hewlett-Packard engineers, and is the second processor implementation of the ItaniumTM processor family (IPF) architecture. This paper describes the methodology developed for testing a complex high-performance microprocessor design. An overview of the processor is presented, along with the goals for the test methodology. Details of the test control blocks, scan methodology, and clocking are given. The scanlatch design, trade-offs and verification processes are discussed, along with some details of ATPG modeling and memory array testing. Finally, some results are presented
Keywords :
automatic test pattern generation; clocks; integrated circuit design; integrated circuit testing; microprocessor chips; ATPG modeling; Hewlett-Packard; Intel; Itanium processor family architecture; McKinley processor; clocking; joint design effort; memory array testing; microprocessor design; processor implementation; scan methodology; scanlatch design; test control blocks; test methodology; testing; verification processes; Circuit synthesis; Circuit testing; Clocks; Computer architecture; Design engineering; Engines; Manufacturing processes; Microarchitecture; Microprocessors; Process design;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966676
