A low-power VLSI design methodology for high bit-rate data communications over UTP channel

Author

Goez, M. ; Shanbhag, Naresh R.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

6

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

474

Abstract

Presented in this paper is a systematic methodology to design low-power integrated transceivers for broadband data communications over unshielded twisted-pair (UTP) channels. The design methodology is based upon two algorithmic low-power techniques referred to as Hilbert transformation and strength reduction and a high-speed pipelining technique referred to as relaxed look-ahead transformation. Finite-precision requirements and power savings are presented. The application of these techniques to design low- and high-speed 155.52 Mb/s ATM-LAN and 51.84 VDSL transceivers is illustrated

Keywords

Hilbert transforms; VLSI; data communication equipment; integrated circuit design; pipeline processing; transceivers; twisted pair cables; ATM-LAN; Hilbert transformation; UTP channel; VDSL; algorithm; broadband data communication; high-speed pipelining; integrated transceiver; look-ahead transformation; low power VLSI design; strength reduction; unshielded twisted-pair channel; Broadband communication; DSL; Data communication; Design methodology; Digital communication; Frequency; Propagation losses; Transceivers; Very large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.705314

Filename

705314