Title :
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo
Author :
Vandling, Gilbert
Abstract :
This paper describes the approach used to model the memory circuits contained in the Gekko microprocessor and the delay testing that was done at functional speeds using these models. The combination of accurate memory models and good delay testing has produced a tenfold reduction in customer returns for this chip compared with prior PowerPC programs
Keywords :
automatic test pattern generation; delay estimation; fault diagnosis; integrated circuit modelling; integrated circuit testing; microprocessor chips; AC LSSD fallout; Gekko microprocessor; IBM PowerPC derivative; Nintendo; customer returns reduction; delay testing; functional speeds; memory circuit modeling; pattern generation; transition fault coverage; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Clocks; Costs; Delay; Hardware; Logic testing; Microprocessors;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966678
