Title :
Automated synthesis of systems with interacting asynchronous (self-timed) and synchronous components
Author :
Subrahmanyam, P.A.
Author_Institution :
AT&T Bell Lab., Holmdel, NJ, USA
Abstract :
Techniques for the specification and automated synthesis of systems containing a mixture of synchronous and asynchronous (self-timed) subsystems are discussed. The input to the system consists of the behavior and performance specifications for a set of processes that interact by communicating over channels connecting typed ports; a graphical perspective on temporal constraints is provided via a timing diagram editor. Factors that influence the decomposition of the overall system into subprocesses and the choice of implementation styles include external interface constraints, system performance requirements, and system design complexity. Syntax-directed transformations are applied to the initial specification to generate a hierarchical structural description. Existing logic optimization and physical layout tools are then used to produce either standard cell or custom CMOS layouts. Fragments of the design of a processor interface board are used to illustrate various concepts
Keywords :
CMOS integrated circuits; asynchronous sequential logic; logic CAD; CMOS layouts; automated synthesis; external interface constraints; hierarchical structural description; interacting asynchronous and synchronous components; processor interface board; self-timed components; specification; system design complexity; system performance requirements; temporal constraints; timing diagram editor; CMOS logic circuits; Calculus; Clocks; Hardware; Integrated circuit synthesis; Joining processes; Large scale integration; Protocols; System performance; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63373
