Title :
Too much delay fault coverage is a bad thing
Abstract :
Delay fault test application via enhanced scan and skewed load techniques is shown to allow scan-based delay tests to be applied that are unrealizable in normal operation. Rather than higher coverage being a positive feature, it is shown to have negative impact on yield and designer productivity. The use of functionally justified tests is defended by both a motivating example and data from benchmark circuits. Implications on overhead, yield, timing optimization, and test debug are discussed
Keywords :
automatic test pattern generation; boundary scan testing; delays; design for testability; fault diagnosis; flip-flops; integrated circuit testing; integrated circuit yield; logic testing; sequential circuits; timing; benchmark circuits; delay fault coverage; design-for-testability features; designer productivity; enhanced scan; flip-flops; functionally justified tests; logical operation; scan-based delay tests; skewed load techniques; test debug; timing behavior; timing optimization; yield; Circuit faults; Circuit testing; Clocks; Delay; Electrical fault detection; Fault detection; Flip-flops; Logic; Productivity; Timing;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966682
